1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly to an improvement of the equalize timing of a signal transmission line for transmitting a data signal provided from a bit line. This invention has particular applicability to a serial access memory.
2. Description of the Background Art
The recent usage of semiconductor memories in various equipments have led to the need of various features. In addition to the basic features of a semiconductor memory to store an applied (or a predetermined) data and read out the stored data, the feature for access has also become necessary. Particularly, serial access, i.e. serial reading and/or serial writing of data signals, has become necessary to process video signals or image signals at a high speed.
A field memory and a video RAM, for examples, are known as random access memories (RAM) having serial access feature. In a field memory, an applied data signal is written in series into a memory cell, and the stored data signal is read out in the order that it was written. A field memory is often used as a delay circuit for video signal processing since it has a memory capacity that can store digital pixel signals of one screen of a television, for example.
A video RAM comprises a random access port and a serial access port. Through a random access port, an applied data signal is stored in an externally specified memory cell, and the stored data signal is read out from an externally specified memory cell. Through a serial access port, an applied data signal is stored in an externally specified memory cell row in series, and the stored data signal is read out in series from an externally specified memory cell row. The random access port is frequently used to carry out the image signal processing at a high speed. The serial access port is used to supply the processed signal, i.e. the stored image signal, to an image display device such as a CRT at a high speed.
A first-in-first-out (FIFO) memory, though not a RAM, is also known, for storing applied data signals in series and reading out in series the stored data signal in the order that they were stored.
It is appreciated that the above semiconductor memories are common in the point that they have a feature for reading out in series the data signal stored in a memory cell. Although the present invention is applicable to a semiconductor memory, particularly to a serial access memory having serial access feature, a field memory will be taken as an example in the following to simplify the description.
A field memory is widely used for the purpose of processing video signals and image signals in television technology and video tape recorders (VTRs). A video signal is converted into a digital signal by an A/D converter to be stored temporarily within a serial access memory. Various image processing is carried out to the stored video signals to realize the features of noise reduction and interlace display in image display. This processing gives rise to the need of image processing in a higher speed using field memory. Accordingly, there is a strong demand for improvement in the operation speed of serial access memory. For example, a time period of less than 30 ns is required as the cycle time of a serial out clock signal used for reading in series stored data. Some recently developed field memories have a cycle time as low as 10 ns. The trend in increasing operation speed in serial access memories is expected to grow as the request for high speed operation of image processing becomes great.
FIG. 4 is a block diagram of a field memory showing the background of the present invention. Referring to FIG. 4, this field memory comprises a memory cell array 1 having a plurality of memory cells arranged in rows and columns, a row decoder 2 for selecting an externally specified memory cell row, a column decoder 3 for selecting an externally specified memory cell column, and a sense amplifier 7 for amplifying a data signal read out from a memory cell. A serial selector 8 for data input is connected to column decoder 3.
In writing operation, input buffer 9 receives externally applied serial input data SID1-SID6 to provide the same to a data register 10. Data register 10 holds the applied parallel data to provide the same to memory cell array 1 in response to an output signal generated from serial selector 8. Row decoder 2 selects one word line specified by an externally applied address signal, whereby the data provided from data register 10 is written into one memory cell row.
In reading operation, row decoder 2 selects a word line specified by an externally applied address signal. The data signals stored in the memory cell row connected to the selected word line are applied to a bit line (not shown) and amplified by sense amplifier 7. The parallel data signals amplified by sense amplifier 7 are provided to a data register 4 to be held therein. Serial selector 5 responds to an externally applied serial output clock signal SOC to sequentially select a latch circuit provided in data register 4. In other words, data register 4 responds to a serial selecting signal SS generated from serial selector 5 to provide the held or latched data signal sequentially to a serial bus SB. An output buffer 6 is connected to data register 4 via serial bus SB. Therefore, the data signals read out from a memory cell row in memory cell array 1 are provided as serial output data SOD1-SOD6 via output buffer 6.
The other circuits in the field memory will be explained hereinafter briefly. An instruction/address buffer 11 receives externally applied instruction signals IR1-IR7/address signals A0-A8. The received address signals A0-A8 are applied to row decoder 2, column decoder 3, a row address counter 12 for input, and a row address counter 13 for output. Row decoder 2 responds to a count signal from address counter 12 or 13 to select a memory cell row, i.e., a word line. In refresh mode, row decoder 2 also responds to a count signal from a row address counter 14 for refresh to select a word line. An instruction signal received by instruction/address buffer 11 is held within an instruction register 15. An instruction decoder 16 receives an instruction signal held in instruction register 15 to decode the same. Instruction decoder 16 generates various control signals for the operation of the field memory according to the externally applied instruction. The field memory comprises a timing signal generating circuit 17 for generating a timing signal to operate the above circuits in synchronization.
FIG. 5 is a circuit diagram of memory cell array 1, sense amplifier 7, and data register 4 of FIG. 4. Although FIG. 5 shows the circuits associated with two memory cell columns, only the circuits associated with one memory cell column will be explained to simplify the description. Referring to FIG. 5, a bit line BLa and a bit line BLb form a bit line pair to transmit data signals inverted with respect to each other. An NMOS transistor Q1 is operated in response to a bit line hold signal .phi.1 to hold the potentials of the bit line pair BLa, BLb at a predetermined potential (Vcc/2). In other words, bit line pair BLa, BLb is set to potential Vcc/2 when transistor Q1 is turned on, since signal .phi.2 always has a potential of Vcc/2. An NMOS transistor Q2 is connected between bit lines BLa and BLb to equalize the bit line pair BLa, BLb in response to an equalize signal .phi.3. Dummy memory cells DC1 and DC2 are connected to bit lines BLa and BLb, respectively. Switching transistors Q3 and Q4 are operated in response to dummy word line signals .phi.5 and .phi.4, respectively.
There are two memory cells MC1 and MC3 connected to bit line BLa, and two memory cells MC2 and MC4 connected to bit line BLb. For example, memory cell MC1 comprises an NMOS transistor Q5 for switching and a capacitor C3 for storing a data signal. Transistor Q5 operates in response to a word line signal .phi.7 provided from a row decoder (not shown). Switching transistor Q6 forming memory cell MC2 operates in response to another word line signal .phi.6.
A sense amplifier 7 is constituted by PMOS transistors Q7 and Q9, and NMOS transistors Q8 and Q10. A plurality of sense amplifiers provided along the row direction are activated in response to activation signals .phi.8 and .phi.9. NMOS transistors Q11 and Q12 are connected to the corresponding bit lines of BLa and BLb, respectively, to transmit a bit line signal to data register circuit 4 in response to a transfer signal .phi.10.
One latch circuit forming data register circuit 4 comprises NMOS transistors Q13 and Q15, and PMOS transistors Q14 and Q16. Each of the latch circuits provided along the row direction is connected between power supply potential Vcc and ground potential.
One serial transfer circuit formed by four NMOS transistors Q17-Q20 responds to a serial selecting signal .phi.14 generated from serial selector 5 shown in FIG. 4 to transfer data signals .phi.21 and .phi.21 latched by the aforementioned one latch circuit to serial bus lines SBai and SBbi. In other words, one of transistors Q17 and Q18 is turned on in response to signal .phi.21 or signal .phi.21. Also, transistors Q19 and Q20 are turned on in response to serial selecting signal .phi.14 to provide a data signal latched in the latch circuit to serial bus lines SBai and SBbi.
FIG. 6 is a timing chart for explaining the operation of the circuits of FIG. 5. Referring to FIGS. 5 and 6, the reading operation will be explained hereinafter. Signal IRS in FIG. 6 indicates an externally applied instruction strobe signal. Signal CAS indicates a column address strobe signal. Signal RAS indicates a row address strobe signal. Signal IRE indicates an instruction enable signal. These signals are applied from an external source, as shown in FIG. 4, to control the reading and writing operations of the field memory. In the following description, signals IRS and CAS are represented by signal .phi.23, and signals RAS and IRE are represented by signal .phi.24.
Following the fall of signal .phi.23 at time t1, signal .phi.24 also falls at time t2. Signals .phi.1 and .phi.3 respond to the fall of signal .phi.24 to fall at times t3 and t4, respectively. Transistors Q1 and Q2 are at the ON state since signals .phi.1 and .phi.3 are respectively at logical high (high level) until the respective times of t3 and t4. Therefore, the pair of bit lines BLa and BLb are equalized (set to Vcc/2) till time t4, and then held at a floating state.
At time t5, word line signal .phi.7 rises. Because switching transistor Q5 of memory cell MC1 is turned on in response to signal .phi.7 at a high level, a small potential difference appears between bit lines BLa and BLb. After time t6, activation signals .phi.8 and .phi.9 attain a high level and a low level, respectively, to activate sense amplifier circuit 7. Therefore, the small potential difference between bit lines BLa and BLb is amplified by sense amplifier circuit 7. The rise of transfer signal .phi.10 at time t7 causes transistors Q11 and Q12 to be turned on, whereby the potential difference between bit lines BLa and BLb (i.e. the read out data signal) is provided to latch circuit 4 via transistors Q11 and Q12. Latch circuit 4 latches the applied data signals .phi.21 and .phi.21.
Although the reading operation is described for one memory cell column in the above description, a similar reading operation is carried simultaneously for the other memory columns in memory cell array 1. The data signals read out from each memory cell column are held in the corresponding latch circuit, i.e. in data register 4. The data signals held in data register 4 are serially provided to a serial bus line pair SBai and SBbi in response to a serial selecting signal (for example .phi.14) applied from serial selector 5.
FIG. 7 is a circuit diagram of output buffer 6 of FIG. 4. The field memory of FIG. 4 comprises six serial output data terminals SOD1-SOD6. This means that serial bus SB provided between data register 4 and output buffer 6 comprises six serial bus line pairs. The circuit of FIG. 7 is shown connected to one of the serial bus line pairs, i.e. the i-th serial bus line pairs SBai, SBbi. Serial bus lines SBai and SBbi of FIG. 7 are connected to serial bus lines SBai and SBbi of FIG. 5, respectively.
Referring to FIG. 7, output buffer 6 comprises an equalize circuit 60i for equalizing the serial bus line pair SBai, SBbi, a preamplifier circuit 61i, an inverter circuit 62i, two latch circuits 63i and 64i, and a main amplifier 65i. The output of main amplifier 65i is connected to the i-th serial output data terminal SODi.
Equalize circuit 60i comprises three PMOS transistors Q26, Q27 and Q28 operated in response to equalize signal .phi.19. PMOS transistors Q29 and Q30 are connected between serial bus lines SBai and SBbi and the corresponding data bus lines of DBai and DBbi. Transistors Q29 and Q39 have their gates grounded. A PMOS transistor Q31 for equalization is connected between data bus lines BDai and DBbi. Transistor Q31 is operated also in response to equalize control signal .phi.19.
Preamplifier 61i comprises a current mirror type amplifier 21 and a cross coupled type amplifier 22 each connected to data bus line pair DBai, DBbi. Current mirror type amplifier 21 is formed of PMOS transistors Q32 and Q33, and NMOS transistors Q34 and Q35. Cross coupled type amplifier 22 is formed of NMOS transistors Q36 and Q37. Amplifiers 21 and 22 are activated in response to preamplifier enable signal .phi.18.
Inverter circuit 62i comprises a PMOS transistor Q39 and NMOS transistors Q40 and Q41 connected in series between power supply potential Vcc and ground potential. Transistors Q39 and Q40 have their gates connected to receive data signal DS1 provided from preamplifier 61i. Inverter circuit 62i is activated also in response to enable signal .phi.18. NMOS transistors Q47 and Q48 serving as transfer gates are provided in the preceding stages of latch circuits 63i and 64i, respectively. Transistor Q47 is turned on in response to signal .phi.18. Transistor Q48 is turned on in response to signal .phi.25.
FIG. 8 is a timing chart for explaining the operation of the circuit of FIG. 7. Referring to FIGS. 7 and 8, the operation thereof will be explained hereinafter. Referring to FIG. 8, one stored data signal is read from one memory cell column during one cycle period of a serial out clock signal SOC. It is understood that six data signals are provided simultaneously within one cycle period via serial output data terminals SOD1-SOD6 of the field memory of FIG. 4. In response to serial out clock signal SOC, clock signal .phi.16 is generated. In response to clock signal .phi.16, signal .phi.17 is generated. In response to signal .phi.17, signals .phi.14, .phi.18 and .phi.19 are generated.
Since equalize signal .phi.19 is at a low level before time t21, transistors Q26, Q27 and Q28 forming equalize circuit 60i are at the ON state. Serial bus lines SBai, SBbi are equalized and set to power supply potential Vcc. At time t21, serial selecting signal .phi.14 and equalize signal .phi.19 rise. Transistors Q19 and Q20 of FIG. 5 turned on in response to serial selecting signal .phi.14 of a high level causes a small potential difference between serial bus lines SBai and SBbi. This small potential difference is transmitted to data bus lines DBai and DBbi via transistors Q29 and Q30 of FIG. 7. Transistors Q29 and Q30 are provided for the purpose of increasing the speed of amplification operation of preamplifier 61i.
At time t22, preamplifier enable signal .phi.18 rises. Therefore, current mirror type amplifier 21 and cross coupled type amplifier 22 provided in preamplifier 61i and inverter circuit 62i are activated. This causes the small potential difference on data bus line pair DBai, DBbi to be amplified, whereby the amplified data signal DS1 is provided to inverter circuit 62i.
Data signal DS1 is inverted by inverter circuit 62i to be provided to main amplifier 65i via two latch circuits 63i and 64i. The data signal latched by latch circuit 63i is shown in FIG. 8 as signal DS2. The data signal applied to main amplifier 65i is amplified therein to be provided to an external source via serial out data terminal SODi.
The circuits for generating various clock signals or control signals used to control the above described operations will be explained hereinafter briefly. FIGS. 9-11 are circuit diagrams of control circuits 100, 200, 300 and 400 for generating clock signals .phi.16, .phi.17, .phi.18, .phi.19 and .phi.25. These control circuits 100, 200, 300 and 400 are provided in timing signal generating circuit 17 of FIG. 4.
Referring to FIGS. 9A and 9B, control circuit 100 comprises an input buffer 101 formed by a Schmitt circuit, an NOR gate 102, inverters 103-108, an NOR gate 109, and an NMOS transistor Q42. Input buffer 101 comprises PMOS transistors Q21, Q22 and Q25, NMOS transistors Q23 and Q24, and an inverter 111. Input buffer 101 is connected to receive an externally applied serial out clock signal SOC. Control circuit 100 responds to the applied signal SOC to generate a clock signal .phi.16 having a pulse width determined by a delay circuit formed of inverters 103-104 and a capacitor 110. Since input buffer 101 is implemented by a Schmitt circuit, an output signal having an MOS logic amplitude can be supplied to NOR gate 102, even though the externally applied signal SOC has a TTL amplitude.
Referring to FIG. 10, control circuit 200 comprises NAND gates 201 and 202, inverters 203-209, and a capacitor 210. NAND gate 201 receives clock signal .phi.16 provided from control circuit 100 of FIG. 9. In response to the applied clock signal .phi.16, control circuit 200 generates clock signal .phi.17 having a pulse width determined by a delay circuit formed of inverters 205 and 206, and capacitor 210. Clock signal .phi.17 is used to generate the aforementioned serial selecting signal .phi.14, and is also applied to control circuit 300.
Control circuit 300 comprises an NAND circuit 301, inverters 302-309, and capacitors 310 and 311. Control circuit 300 generates preamplifier enable signal .phi.18 and equalize signal .phi.19 used to control the circuit of FIG. 7.
Referring to FIG. 11, control circuit 400 comprises inverters 401-405, an NAND gate 406, an NOR gate 407, and a capacitor 409. Control circuit 409 responds to clock signal .phi.16 provided from circuit 100 of FIG. 9 to generate clock signal .phi.25 for controlling transfer gate transistor Q48 of FIG. 7.
The frequency of externally applied serial out clock signal SOC is becoming higher to comply with the request of higher operation speed of field memories, as mentioned before. Therefore, the cycle period T of serial out clock signal SOC of FIG. 8 has become shorter, leading to the following problems.
A higher frequency of signal SOC requires a higher frequency of equalize signal .phi.19 for equalizing serial bus lines SBai and SBbi. This means that the equalize time period Te of FIG. 8 (i.e. the time period of signal .phi.19 at a low level) becomes shorter. The equalizations of serial bus lines SBai and SBbi, and data bus lines DBai and DBbi may not be carried out sufficiently during this shorter equalize time period Te. Particularly, the long wiring length of serial bus lines SBai and SBbi is responsible for the charging/discharging of equalization requiring a long time period. Erroneous reading will occur if preamplifier 61i commences the next amplifying operation in response to enable signal .phi.18 in the case where serial bus lines SBai and SBbi are not yet completely equalized. More specifically, the preceding read out data signal remains on serial bus line pair SBai, SBbi because serial bus lines SBai and SBbi are not equalized sufficiently. The newly read out data signal will be affected by the remaining data signal to result in erroneous reading.